1. Field of the Invention
The present invention relates to a multiprocessor system having a plurality of processors each including a primary cache and a secondary cache shared by the processors, and a cache control method, and, more particularly to a multiprocessor system, a processor, and a cache control method that can prevent competitions for data acquisition by a plurality of caches, and reduce delay in data transfer between caches.
2. Description of the Related Art
Generally, in an information processor, frequently used data is stored in a cache memory separate from a main memory, to improve processing speed. While the cache memory has a smaller capacity than that of the main memory, high-speed access is possible. Therefore, by storing the frequently used data in the cache memory, while replacing the data at any time, greater processing speed can be achieved.
To further achieve greater processing speed, the cache memory is provided hierarchically, and at the time of performing the processing, the primary cache having the highest speed (hereinafter, “L1 cache”) is first accessed, and if there is no desired data in the L1 cache, then the secondary cache (hereinafter, “L2 cache”) having the next highest speed is accessed.
On the other hand, to improve processing performance of the information processor, a plurality of processors can be mounted on one information processor. In recent years, as one type of such a multiprocessor system, an on-chip multiprocessor system in which a plurality of processors are mounted on one chip has been realized.
When the multiprocessor system is employed, the L2 cache shared by respective processors can be provided, separately from the L1 cache in each processor (for example, see Japanese Patent Application Laid-open No. 2002-373115).
In the multiprocessor system, if a cache miss occurs simultaneously relating to the same data in the L1 cache in each processor, a plurality of processors can access the shared L2 cache simultaneously to cause competitions for data acquisition.
A state where an L1 cache #1 and an L1 cache #2 compete for data A is explained below with reference to FIGS. 4A to 4F. It is assumed here that a store request indicating rewrite of data A is issued from a command controller (not shown) in each processor to the L1 cache #1 and the L1 cache #2, respectively.
As shown in FIG. 4A, because the data A is not stored in the L1 cache #1 and the L1 cache #2, the cache miss occurs, and a move in (hereinafter, abbreviated as “MI”) request for requesting MI of the data A is made simultaneously to an L2 cache controller that controls the L2 cache.
At this time, for example, if priority of the L1 cache #1 is high, as shown in FIG. 4B, the data A is transferred from the L2 cache controller to the L1 cache #1. Further, because the MI request of the data A is also made to the L2 cache controller from the L1 cache #2, upon transfer of the data A to the L1 cache #1, a move out (hereinafter, abbreviated as “MO”) command for moving the data A out from the L1 cache #1 is issued.
In the L1 cache #1, a store process of the data A has not been completed; however, according to the MO command from the L2 cache controller, as shown in FIG. 4C, an MO request for requesting MO of the data A is made, and the data A is transferred to the L2 cache controller. Simultaneously, the L2 cache controller transfers the data A to the L1 cache #2.
In the L1 cache #1 to which the data A is supposed to be transferred, a store request of the data A is made again. However, because the data A has been already transferred to the L1 cache #2, a cache miss occurs again in the L1 cache #1. Therefore, as shown in FIG. 4D, an MI request is made from the L1 cache #1 to the L2 cache controller, and an MO command is issued from the L2 cache controller to the L1 cache #2.
In the L1 cache #2, the store process of the data A has not been completed; however, according to the MO command from the L2 cache controller, as shown in FIG. 4E, an MO request for requesting MO of the data A is made, and the data A is transferred to the L2 cache controller. Simultaneously, the L2 cache controller transfers the data A to the L1 cache #1.
In the L1 cache #2 to which the data A is supposed to be transferred, a store request of the data A is made again. However, because the data A has been already transferred to the L1 cache #1, a cache miss occurs again in the L1 cache #2. Therefore, as shown in FIG. 4F, an MI request is made from the L1 cache #2 to the L2 cache controller, and an MO command is issued from the L2 cache controller to the L1 cache #1.
Thereafter, the state returns to the state in FIG. 4C, and any of the processor having the L1 cache #1 and the processor having the L1 cache #2 cannot complete the store process of the data A.
To prevent such a situation, a method in which after the MI request is once made and the data is transferred to the L1 cache, MO is prohibited in the L1 cache for a while can be considered. That is, for example, as shown in FIG. 5, the MI request obtains priority of a pipeline process, and after a process of predetermined P cycle is complete, a counter starts counting up of the predetermined cycle (in FIG. 5, 31 cycles). Thereafter, a process of a predetermined T cycle, a process of a predetermined M cycle, a process of a predetermined B cycle, and a process of a predetermined R cycle are performed with respect to the MI request, and data is stored in the L1 cache.
At this time, when the MO request obtains the priority of the pipeline process immediately after the MI request, for the MO request, because the counter is executing counting up, the process is suspended in the B cycle. Therefore, while the counter is executing counting up, the data is not transferred from the L1 cache, and the store process of the data can be performed in this period.
In this method, however, because data transfer from the L1 cache is prohibited while the counter is executing counting up, MO is not executed also for data irrelevant to the store process, thereby causing a problem that delay occurs in data transfer between caches.